數字集成電路設計：從VLSI體係結構到CMOS製造（英文版） [Digital Integrated Circuit Design From VLSI Architectures to CMOS Fa 下載 mobi epub pdf 電子書 2024

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　　今天，集成電路設計技術高速發展，在各個領域得到廣泛應用，已經成為一種橫跨多學科的技術。《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》從架構與算法講起，介紹瞭功能驗證、VHDL建模、同步電路設計、異步數據獲取、能耗與散熱、信號完整性、物理設計、設計驗證等必備技術，還講解瞭VLSI經濟與項目管理，並簡單闡釋瞭CMOS技術的基礎知識，全麵覆蓋瞭數字集成電路的整個設計開發過程。
　　作為一本教科書，《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》嚮工程專業學生展示瞭數字VLSl設計之美。揭示瞭各種技術難點，使他們避免重復前人的錯誤；作為一本技術參考書，《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》內容全麵，豐富的錶格、清單、電路圖和個案研究能夠幫助正在開發硬件電路的在職工程師更好地完成自己的設計。
　　《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》特點
　　·涵蓋瞭數字VLSI設計的大部分問題
　　·從算法設計到晶圓生産，以自頂嚮下方式一一講述
　　·重點闡釋瞭流行的CMOS技術和靜態電路
　　·全麵覆蓋數字VLSI設計者需要知道的半導體物理知識
　　·圖文並茂，深度體現課堂教學和實際設計項目驗證的思想

內容簡介

　　《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》從架構與算法講起，介紹瞭功能驗證、VHDL建模、同步電路設計、異步數據獲取、能耗與散熱、信號完整性、物理設計、設計驗證等必備技術，還講解瞭VLSI經濟運作與項目管理，並簡單闡釋瞭CMOS技術的基礎知識，全麵覆蓋瞭數字集成電路的整個設計開發過程。
　　《數字集成電路設計：從VLSI體係結構到CMOS製造(英文版)》既可作為高等院校微電子、電子技術等相關專業高年級師生和研究生的參考教材，也可供半導體行業工程師參考。

作者簡介

　　Hubert Kaeslin，1985年於瑞士蘇黎世聯邦理工學院獲得博士學位，現為該校微電子設計中心的負責人，具有20多年教授VLSI的豐富經驗。

內頁插圖

目錄

Chapter 1　Introduction to Microelectronics　1
1.1　Economic impact　1
1.2　Concepts and terminology　4
1.2.1　The Guinness book of records point of view　4
1.2.2　The marketing point of view　5
1.2.3　The fabrication point of view　6
1.2.4　The design engineers point of view　10
1.2.5　The business point of view　17
1.3　Design flow in digital VLSI　18
1.3.1　The Y-chart， a map of digital electronic systems　18
1.3.2　Major stages in VLSI design　19
1.3.3　Cell libraries　28
1.3.4　Electronic design automation software　29
1.4　Field-programmable logic　30
1.4.1　Configuration technologies　30
1.4.2　Organization of hardware resources　32
1.4.3　Commercial products　35
1.5　Problems　37
1.6　Appendix I： A brief glossary of logic families　38
1.7　Appendix II： An illustrated glossary of circuit-related terms　40

Chapter 2　From Algorithms to Architectures　44
2.1　The goals of architecture design　44
2.1.1　Agenda　45
2.2　The architectural antipodes　45
2.2.1　What makes an algorithm suitable for a dedicated VLSI architecture?　50
2.2.2　There is plenty of land between the architectural antipodes　53
2.2.3　Assemblies of general-purpose and dedicated processing units　54
2.2.4　Coprocessors　55
2.2.5　Application-specific instruction set processors　55
2.2.6　Configurable computing　58
2.2.7　Extendable instruction set processors　59
2.2.8　Digest　60
2.3 A　transform approach to VLSI architecture design　61
2.3.1　There is room for remodelling in the algorithmic domain　 62
2.3.2　...and there is room in the architectural domain　64
2.3.3　Systems engineers and VLSI designers must collaborate　64
2.3.4　A graph-based formalism for describing processing algorithms　65
2.3.5　The isomorphic architecture　66
2.3.6　Relative merits of architectural alternatives　67
2.3.7　Computation cycle versus clock period　69
2.4　Equivalence transforms for combinational computations　70
2.4.1　Common assumptions　71
2.4.2　Iterative decomposition　72
2.4.3　Pipelining　75
2.4.4　Replication　79
2.4.5　Time sharing　81
2.4.6　Associativity transform　86
2.4.7　Other algebraic transforms　87
2.4.8　Digest　87
2.5　Options for temporary storage of data　89
2.5.1　Data access patterns　89
2.5.2　Available memory configurations and area occupation　89
2.5.3　Storage capacities　90
2.5.4　Wiring and the costs of going off-chip　91
2.5.5　Latency and timing　91
2.5.6　Digest　92
2.6　Equivalence transforms for nonrecursive computations　93
2.6.1　Retiming　94
2.6.2　Pipelining revisited　95
2.6.3　Systolic conversion　97
2.6.4　Iterative decomposition and time-sharing revisited　98
2.6.5　Replication revisited　98
2.6.6　Digest　99
2.7　Equivalence transforms for recursive computations　99
2.7.1　The feedback bottleneck　100
2.7.2　Unfolding of first-order loops　101
2.7.3　Higher-order loops　103
2.7.4　Time-variant loops　105
2.7.5　Nonlinear or general loops　106
2.7.6　Pipeline interleaving is not an equivalence transform　109
2.7.7　Digest　111
2.8　Generalizations of the transform approach　112
2.8.1　Generalization to other levels of detail　112
2.8.2　Bit-serial architectures　113
2.8.3　Distributed arithmetic　116
2.8.4　Generalization to other algebraic structures　118
2.8.5　Digest　121
2.9　Conclusions　122
2.9.1　Summary　122
2.9.2　The grand architectural alternatives from an energy point of view　124
2.9.3　A guide to evaluating architectural alternatives　126
2.10　Problems　128
2.11　Appendix I： A brief glossary of algebraic structures　130
2.12　Appendix II： Area and delay figures of VLSI subfunctions　133

Chapter 3　Functional Verification　136
3.1　How to establish valid functional specifications　137
3.1.1　Formal specification　138
3.1.2　Rapid prototyping　138
3.2　Developing an adequate simulation strategy　139
3.2.1　What does it take to uncover a design flaw during simulation?　139
3.2.2　Stimulation and response checking must occur automatically　140
3.2.3　Exhaustive verification remains an elusive goal　142
3.2.4　All partial verification techniques have their pitfalls　143
3.2.5　Collecting test cases from multiple sources helps　150
3.2.6　Assertion-based verification helps　150
3.2.7　Separating test development from circuit design helps　151
3.2.8　Virtual prototypes help to generate expected responses　153
3.3　Reusing the same functional gauge throughout the entire design cycle　153
3.3.1　Alternative ways to handle stimuli and expected responses　155
3.3.2　Modular testbench design　156
3.3.3　A well-defined schedule for stimuli and responses　156
3.3.4　Trimming run times by skipping redundant simulation sequences　159
3.3.5　Abstracting to higher-level transactions on higher-level data　160
3.3.6　Absorbing latency variations across multiple circuit models　164
3.4　Conclusions　166
3.5　Problems　168
3.6　Appendix I： Formal approaches to functional verification　170
3.7　Appendix II： Deriving a coherent schedule for simulation and test　171

Chapter 4　Modelling Hardware with VHDL　175
4.1　Motivation　175
4.1.1　Why hardware synthesis?　175
4.1.2　What are the alternatives to VHDL?　176
4.1.3　What are the origins and aspirations of the IEEE 1076 standard?　176
4.1.4　Why bother learning hardware description languages?　179
4.1.5　Agenda　180
4.2　Key concepts and constructs of VHDL　180
4.2.1　Circuit hierarchy and connectivity　181
4.2.2　Concurrent processes and process interaction　185
4.2.3　A discrete replacement for electrical signals　192
4.2.4　An event-based concept of time for governing simulation　200
4.2.5　Facilities for model parametrization　211
4.2.6　Concepts borrowed from programming languages　216
4.3　Putting VHDL to service for hardware synthesis　223
4.3.1　Synthesis overview　223
4.3.2　Data types　224
4.3.3　Registers， finite state machines， and other sequential subcircuits　225
4.3.4　RAMs， ROMs， and other macrocells　231
4.3.5　Circuits that must be controlled at the netlist level　233
4.3.6　Timing constraints　234
4.3.7　Limitations and caveats for synthesis　238
4.3.8　How to establish a register transfer-level model step by step　238
4.4　Putting VHDL to service for hardware simulation　242
4.4.1　Ingredients of digital simulation　242
4.4.2　Anatomy of a generic testbench　242
4.4.3　Adapting to a design problem at hand　245
4.4.4　The VITAL modelling standard IEEE 1076.4　245
4.5　Conclusions　247
4.6　Problems　248
4.7　Appendix I： Books and Web Pages on VHDL　250
4.8　Appendix II： Related extensions and standards　251
4.8.1　Protected shared variables IEEE 1076a　251
4.8.2　The analog and mixed-signal extension IEEE 1076.1　252
4.8.3　Mathematical packages for real and complex numbers IEEE 1076.2　253
4.8.4　The arithmetic packages IEEE 1076.3　254
4.8.5　A language subset earmarked for synthesis IEEE 1076.6　254
4.8.6　The standard delay format (SDF) IEEE 1497　254
4.8.7　A handy compilation of type conversion functions　255
4.9　Appendix III： Examples of VHDL models　256
4.9.1　Combinational circuit models　256
4.9.2　Mealy， Moore， and Medvedev machines　261
4.9.3　State reduction and state encoding　268
4.9.4　Simulation testbenches　270
4.9.5　Working with VHDL tools from different vendors　285

Chapter 5　The Case for Synchronous Design　286
5.1　Introduction　286
5.2　The grand alternatives for regulating state changes　287
5.2.1　Synchronous clocking　287
5.2.2　Asynchronous clocking　288
5.2.3　Self-timed clocking　288
5.3　Why a rigorous approach to clocking is essential in VLSI　290
5.3.1　The perils of hazards　290
5.3.2　The pros and cons of synchronous clocking　291
5.3.3 數字集成電路設計：從VLSI體係結構到CMOS製造（英文版） [Digital Integrated Circuit Design From VLSI Architectures to CMOS Fa 下載 mobi epub pdf txt 電子書 格式

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